Semiconductors with the ability to operate more efficiently in order to achieve a significant reduction in power consumption are highly desirable. Typically, silicon substrates are used in the manufacture of such devices, however, further development is limited due to the inherent characteristics of silicon. Development of the next generation of semiconductor devices has emphasized the use of materials having a greater hardness and other unique properties. For example, silicon carbide, when compared with silicon oxide, has a higher thermal conductivity, a greater tolerance for radiation, a higher dielectric strength, and is able to withstand greater temperatures, which makes it suitable for a variety of applications. The use of silicon carbide has been limited, however, by semiconductor fabrication technology.
In order to produce silicon carbide semiconductors, the surfaces of the silicon carbide substrates must be polished in order to provide smooth surfaces and to obtain precise dimensions for the surfaces. The properties which make silicon carbide such a useful substrate provide unique challenges in the polishing process. Due to the hardness of silicon carbide, diamond grit is typically used to mechanically polish silicon carbide substrates.
Chemical-mechanical polishing (CMP) techniques are widely used throughout the semiconductor industry in order to polish the current generation of silicon devices. CMP involves the use of a polishing composition (also known as a polishing slurry) containing an abrasive and an aqueous material, which is applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. The polishing composition may also contain an oxidizing agent, which allows for less aggressive mechanical abrasion of the substrate, thus reducing mechanical damage to the substrate caused by the abrading process. The use of such techniques to polish silicon carbide substrates could greatly reduce the costs of manufacturing semiconductors by decreasing polish time and reducing damage to the substrate.
Adaptation of CMP techniques for silicon carbide polishing has been relatively unsuccessful. Polishing compositions containing colloidal silica resulted in low silicon carbide removal rates, thus requiring a lengthy polishing cycle lasting several hours at temperatures of around 50° C., which is likely to result in damage to the silicon carbide substrate. Zhou, et al., J. Electrochemical Soc., 144, p. L161-L163 (1997); Neslen, et al., J. Electronic Materials, 30, p. 1271-1275 (2001). The long polishing cycle adds considerable cost to the process and is a barrier preventing widespread use of silicon carbide within the semiconductor industry. Thus, there remains a need for alternative polishing systems and methods of polishing substrates comprising silicon carbide.